32 lines
950 B
Verilog
32 lines
950 B
Verilog
`timescale 1ns / 1ps
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module hamming(
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input [11:0] code,
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output [7:0] data,
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output [3:0] syndrome
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);
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reg [3:0] rec_check, calc_check;
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reg [11:0] corrected_code;
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always @* begin
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rec_check = { code[7], code[3], code[1], code[0] };
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calc_check[0] = code[2] ^ code[4] ^ code[6] ^ code[8] ^ code[10];
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calc_check[1] = code[2] ^ code[5] ^ code[6] ^ code[9] ^ code[10];
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calc_check[2] = code[4] ^ code[5] ^ code[6] ^ code[11];
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calc_check[3] = code[8] ^ code[9] ^ code[10] ^ code[11];
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end
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always@* begin
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corrected_code = code;
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if (syndrome > 0)
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corrected_code[syndrome - 1] = ~corrected_code[syndrome - 1];
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end
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assign syndrome = calc_check ^ rec_check;
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assign data = { corrected_code[11], corrected_code[10], corrected_code[9], corrected_code[8],
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corrected_code[6], corrected_code[5], corrected_code[4], corrected_code[2] };
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endmodule
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