Add P2 and P3
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106
Project2/pattern_detector.v
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106
Project2/pattern_detector.v
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// Built and tested with icarus verilog
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module PD(
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input clk,
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input reset,
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input enable,
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input [3:0] din,
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output pattern1,
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output pattern2
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);
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reg _pattern1 = 0, _pattern2 = 0;
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reg [3:0] state = 4'b0000;
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parameter Idle=4'b0000, ZeroPressed=4'b1111, Pat1_05=4'b0001, Pat1_053=4'b0010,
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Pat1_0531=4'b0100, Pat2_06=4'b1110, Pat2_061=4'b1101, Pat2_0619=4'b1011;
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// Output based on the current state. Updates outputs immediatley when state changes.
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always@(state)
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begin
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case (state)
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Pat1_0531: begin
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_pattern1 <= 1;
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_pattern2 <= 0;
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end
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Pat2_0619: begin
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_pattern1 <= 0;
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_pattern2 <= 1;
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end
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default: begin
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_pattern1 <= 0;
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_pattern2 <= 0;
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end
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endcase
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end
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// Set the state based on inputs
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always@(posedge clk or posedge reset)
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begin
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if (reset)
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state <= Idle; // Revert to no keys pressed when reset.
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if(enable) begin // Only register a new keypress on clock edges and when enabled
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case(state)
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Idle:
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if (din == 0)
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state <= ZeroPressed;
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ZeroPressed:
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if (din == 5)
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state <= Pat1_05;
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else if (din == 6)
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state <= Pat2_06;
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else if (din == 0)
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state <= ZeroPressed;
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else
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state <= Idle;
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Pat1_05:
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if (din == 3)
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state <= Pat1_053;
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else if (din == 0)
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state <= ZeroPressed;
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else
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state <= Idle;
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Pat1_053:
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if (din == 1)
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state <= Pat1_0531;
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else if (din == 0)
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state <= ZeroPressed;
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else
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state <= Idle;
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Pat1_0531: // Correct code for pattern 1
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if (din == 0)
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state <= ZeroPressed;
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else
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state <= Idle;
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Pat2_06:
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if (din == 1)
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state <= Pat2_061;
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else if (din == 0)
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state <= ZeroPressed;
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else
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state <= Idle;
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Pat2_061:
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if (din == 9)
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state <= Pat2_0619;
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else if (din == 0)
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state <= ZeroPressed;
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else
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state <= Idle;
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Pat2_0619: // Correct code for pattern 2
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if (din == 0)
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state <= ZeroPressed;
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else
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state <= Idle;
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default:
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state <= Idle;
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endcase
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end
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end
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// Drive wire outputs with internal registers holding output for state
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assign pattern1 = _pattern1;
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assign pattern2 = _pattern2;
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endmodule
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109
Project3/se.v
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109
Project3/se.v
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// Built and tested with Icarus Verilog
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module SE #(
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parameter [7:0] DATAWIDTH = 8,
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parameter [7:0] ARRAYLENGTH = 10
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)
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(
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input clk,
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input [(DATAWIDTH * ARRAYLENGTH) - 1 : 0] array_in,
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input valid_in,
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output [(DATAWIDTH * ARRAYLENGTH) - 1 : 0] array_out,
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output valid_out
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);
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parameter EVEN_ARR_LEN = ARRAYLENGTH % 2 == 0;
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reg [DATAWIDTH - 1: 0] r [0 : ARRAYLENGTH - 1]; // Registers for use between stages
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wire [DATAWIDTH - 1: 0] input_array [0 : ARRAYLENGTH - 1]; // Input represented as array of vectors
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wire [DATAWIDTH - 1 : 0] even_cas_out [0 : ARRAYLENGTH - 1]; // compare and swap output 1 array
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wire [DATAWIDTH - 1 : 0] odd_cas_out [0 : ARRAYLENGTH - 1]; // compare and swap output 2 array
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reg output_valid = 1'b0;
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integer counter = 0; // Handles state of the sorting module
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always@(posedge clk)
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begin
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if (0 == counter) begin // Stage for when sorter has not been given any valid data.
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output_valid <= 0;
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if (1 == valid_in) begin
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// Clock the inputs if we have valid data.
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for (integer i = 0; i < ARRAYLENGTH; i = i + 1) begin
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r[i] <= input_array[i];
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end
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counter <= 1; // Move to next stage.
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end
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end
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else if (1 == valid_in) begin
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counter <= 0;
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end
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else begin
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// Clock the output from even stage at end of each cycle
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for (integer i = 0; i < ARRAYLENGTH; i = i + 1) begin
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r[i] <= even_cas_out[i];
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end
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// Reset state and indicate that output is valid
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if (((ARRAYLENGTH + 1) / 2) == counter) begin
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counter <= 0;
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output_valid <= 1;
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end
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else
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counter <= counter + 1; // Need more clock cycles to sort
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end
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end
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// Generate odd stage compare and swap elements
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genvar odd;
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generate
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// Odd length arrays pass first element through odd CAS stage
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if (!EVEN_ARR_LEN) assign odd_cas_out[0] = r[0];
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for (odd = EVEN_ARR_LEN ? 0 : 1; odd < ARRAYLENGTH - 1; odd = odd + 2) begin : g_odd
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compare_and_swap #(.SIZE(DATAWIDTH)) u1 (.i1(r[odd]), .i2(r[odd + 1]),
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.o1(odd_cas_out[odd]), .o2(odd_cas_out[odd + 1]));
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end
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endgenerate
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// Generate even stage compare and swap elements
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genvar even;
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generate
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// Even length arrays pass first element through even CAS stage
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if (EVEN_ARR_LEN) assign even_cas_out[0] = odd_cas_out[0];
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// Last element always passed directly through even CAS stage
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assign even_cas_out[ARRAYLENGTH - 1] = odd_cas_out[ARRAYLENGTH - 1];
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for (even = EVEN_ARR_LEN ? 1 : 0; even < ARRAYLENGTH - 2; even = even + 2)
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begin : g_even
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compare_and_swap #(.SIZE(DATAWIDTH)) u1 (.i1(odd_cas_out[even]),
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.i2(odd_cas_out[even + 1]), .o1(even_cas_out[even]), .o2(even_cas_out[even + 1]));
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end
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endgenerate
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// Get an array of vectors out of the large input vector
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genvar i;
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generate
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for (i = 0; i < ARRAYLENGTH; i = i + 1)
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begin : g1
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assign input_array[i] = array_in[(i * DATAWIDTH) + DATAWIDTH - 1 : i * DATAWIDTH];
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assign array_out[(i * DATAWIDTH) + DATAWIDTH - 1 : i * DATAWIDTH] = r[i];
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end
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endgenerate
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assign valid_out = output_valid;
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endmodule
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// Module to implement compare and swap behaviour
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module compare_and_swap #(
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parameter [7:0] SIZE = 8
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)
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(
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input [SIZE - 1 : 0] i1,
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input [SIZE - 1 : 0] i2,
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output [SIZE - 1: 0] o1,
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output [SIZE - 1: 0] o2
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);
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assign o1 = i1 > i2 ? i1 : i2;
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assign o2 = i1 > i2 ? i2 : i1;
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endmodule
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@@ -1,4 +1,6 @@
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# ece-327
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My solutions to projects in my Digital Hardware Systems course.
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My solutions to projects in my Digital Hardware Systems course. Written in Verilog.
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1. Project 1: Hamming Decoder
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1. Project 1: Hamming Decoder
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2. Project 2: Pattern detector
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3. Project 3: O(n) Sorting
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