106 lines
3.2 KiB
Verilog
106 lines
3.2 KiB
Verilog
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// Built and tested with icarus verilog
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module PD(
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input clk,
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input reset,
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input enable,
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input [3:0] din,
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output pattern1,
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output pattern2
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);
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reg _pattern1 = 0, _pattern2 = 0;
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reg [3:0] state = 4'b0000;
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parameter Idle=4'b0000, ZeroPressed=4'b1111, Pat1_05=4'b0001, Pat1_053=4'b0010,
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Pat1_0531=4'b0100, Pat2_06=4'b1110, Pat2_061=4'b1101, Pat2_0619=4'b1011;
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// Output based on the current state. Updates outputs immediatley when state changes.
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always@(state)
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begin
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case (state)
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Pat1_0531: begin
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_pattern1 <= 1;
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_pattern2 <= 0;
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end
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Pat2_0619: begin
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_pattern1 <= 0;
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_pattern2 <= 1;
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end
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default: begin
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_pattern1 <= 0;
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_pattern2 <= 0;
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end
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endcase
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end
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// Set the state based on inputs
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always@(posedge clk or posedge reset)
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begin
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if (reset)
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state <= Idle; // Revert to no keys pressed when reset.
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if(enable) begin // Only register a new keypress on clock edges and when enabled
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case(state)
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Idle:
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if (din == 0)
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state <= ZeroPressed;
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ZeroPressed:
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if (din == 5)
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state <= Pat1_05;
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else if (din == 6)
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state <= Pat2_06;
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else if (din == 0)
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state <= ZeroPressed;
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else
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state <= Idle;
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Pat1_05:
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if (din == 3)
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state <= Pat1_053;
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else if (din == 0)
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state <= ZeroPressed;
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else
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state <= Idle;
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Pat1_053:
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if (din == 1)
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state <= Pat1_0531;
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else if (din == 0)
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state <= ZeroPressed;
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else
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state <= Idle;
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Pat1_0531: // Correct code for pattern 1
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if (din == 0)
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state <= ZeroPressed;
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else
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state <= Idle;
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Pat2_06:
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if (din == 1)
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state <= Pat2_061;
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else if (din == 0)
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state <= ZeroPressed;
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else
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state <= Idle;
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Pat2_061:
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if (din == 9)
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state <= Pat2_0619;
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else if (din == 0)
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state <= ZeroPressed;
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else
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state <= Idle;
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Pat2_0619: // Correct code for pattern 2
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if (din == 0)
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state <= ZeroPressed;
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else
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state <= Idle;
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default:
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state <= Idle;
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endcase
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end
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end
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// Drive wire outputs with internal registers holding output for state
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assign pattern1 = _pattern1;
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assign pattern2 = _pattern2;
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endmodule |